Análisis y Simulación en Matlab del Método de Detección y Corrección de Errores Reed-Solomon (204,188) Utilizado en la Norma ISDB-TB e Implementación en un FPGA

Abstract

This article seeks to understand the operation of the method of error detection and correction is handled within the ISDB-TB standard. An algorithm for the encoder and decoder using Matlab and subsequent implementation in Spartan 3E FPGA VHDL card is made. In order to facilitate the understanding and use of algorithms is part of a Reed-Solomon (15,9), which will help facilitate mathematical processes that will later be executed in Matlab and with which a userfriendly graphical interface is developed where you can interact with the FPGA card displaying the simulation and thus verify the analysis.